The present invention relates, in general, to the field of equalization of data line pairs in an integrated circuit memory. More particularly, the present invention relates to a method of equalizing extremely long data line pairs in which the distributed resistance and capacitance thereof adversely affects rapid and complete equalization.
Referring now to FIG. 1, a portion of an integrated circuit memory 100 includes a data amplifier 100 for driving a resistive-capacitive data line pair 14, 16. An equalization circuit 12 is used to equalize lines 14 and 16 to an intermediate voltage VEQ, as is known in the art.
Each pair of data lines 14, 16 typically only has one equalization location (“EQ”), as shown in FIG. 1. Referring to FIG. 2, there are typically three devices (M1, M2, and M3) in equalization circuit 12, but they are all attached to the data line pair 14, 16 at roughly the same physical location. This is because the information needed to fully EQ or sense the data line pair is also usually available only at that same location. Furthermore, this is usually the end of data line pair 14, 16. Transistor M1 is used to provide the VEQ voltage to line 14, transistor M3 is used to provide the VEQ voltage to line 16, and transistor M2 is used short out lines 14 and 16 to remove any small voltage difference between the two lines. The “ EQ” control signal is used to initiate equalization. The actual “ EQ” control signal bus is coupled to the gates of P-channel transistors M1, M2, and M3, and is typically only available at one end of the integrated circuit.
Problems with equalization are encountered due to ever-lengthening data lines as memory size and performance demands increase. In modern integrated circuit memory devices, performing the EQ operation from only one end of the data line pair is very inefficient. At the EQ circuit location, the data line pair equalizes very rapidly, but due to resistive-capacitive (“RC”) delays, the far side of the data line pair lags far behind and is very slow to EQ. The problem of inefficient equalization is further exacerbated since the EQ devices substantially turn off once the data line pair is equalized at the point of attachment and no further power is applied. Thus, when the near end gets close to the EQ state, the VDS of the P-channel EQ devices is close to zero, and so no more charge is put into the data lines to continue the EQ process.
What is desired is a circuit and method for quickly and efficiently equalizing data line pairs in an integrated circuit memory or other circuit, so that the adverse affects of distributed resistance and capacitance in long data lines can be overcome.